View MAX1137MEUA_9102378.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hand-held portableapplications medical instruments battery-powered test equipment solar-powered remotesystems received-signal-strength indicators system supervision general description the max1136?ax1139 low-power, 10-bit, multichannelanalog-to-digital converters (adcs) feature internal track/hold (t/h), voltage reference, clock, and an i 2 c-compatible 2-wire serial interface. these devices operate from a single supply of 2.7v to 3.6v (max1137/max1139) or 4.5v to 5.5v (max1136/max1138) and require only 670? at the maximum sampling rate of 94.4ksps. supply current falls below 230? for sampling rates under 46ksps. autoshutdown powers down the devices between conversions, reducing supply current to less than 1? at low throughput rates. the max1136/max1137 have four analog input channels each, while the max1138/max1139 have 12 analog input channels each. the fully differential analog inputs are software configurable for unipolar or bipolar, and single ended or differential operation. the full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1v to v dd . the max1137/ max1139 feature a 2.048v internal reference and themax1136/max1138 feature a 4.096v internal reference. the max1136/max1137 are available in an 8-pin ?ax package. the max1138/max1139 are available in a 16-pin qsop package. the max1136?ax1139 are guaranteed over the extended temperature range (-40? to +85?). for pin-compatible 12-bit parts, refer to the max1236?ax1239 data sheet. for pin-compatible 8-bit parts, refer to the max1036?ax1039 data sheet. applications features ? high-speed i 2 c-compatible serial interface 400khz fast mode 1.7mhz high-speed mode ? single-supply 2.7v to 3.6v (max1137/max1139) 4.5v to 5.5v (max1136/max1138) ? internal reference 2.048v (max1137/max1139) 4.096v (max1136/max1138) ? external reference: 1v to v dd ? internal clock ? 4-channel single-ended or 2-channel fully differential (max1136/max1137) ? 12-channel single-ended or 6-channel fully differential (max1138/max1139) ? internal fifo with channel-scan mode ? low power 670 a at 94.4ksps 230 a at 40ksps 60 a at 10ksps 6 a at 1ksps 0.5 a in power-down mode ? software-configurable unipolar/bipolar ? small packages 8-pin max (max1136/max1137) 16-pin qsop (max1138/max1139) max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs ___________________________________________________ _____________ maxim integrated products 1 ordering information 19-2334; rev 6; 3/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations and typical operating circuit appear at end of data sheet. part temp range pin-package i 2 c slave address max1136 eua+ -40? to +85? 8 ?ax 0110100 max1137 eua+ -40? to +85? 8 ?ax 0110100 max1138 eee+ -40? to +85? 16 qsop 0110101 max1139 eee+ -40? to +85? 16 qsop 0110101 selector guide part input channels internal reference (v) supply voltage (v) inl (lsb) max1136 4 4.096 4.5 to 5.5 1 max1137 4 2.048 2.7 to 3.6 1 max1138 12 4.096 4.5 to 5.5 1 max1139 12 2.048 2.7 to 3.6 1 autoshutdown is a trademark of maxim integrated products, inc. ?ax is a registered trademark of maxim integrated products, inc. + denotes a lead(pb)-free/rohs-compliant package. downloaded from: http:///
max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs 2 __________________________________________________ _____________________________________ absolute maximum ratings electrical characteristics (v dd = 2.7v to 3.6v (max1137/max1139), v dd = 4.5v to 5.5v (max1136/max1138), v ref = 2.048v (max1137/max1139), v ref = 4.096v (max1136/max1138), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?. see tables 1? for programming notation.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ..............................................................-0.3v to +6v ain0?in11, ref to gnd ............-0.3v to the lower of (v dd + 0.3v) and 6v sda, scl to gnd.....................................................-0.3v to +6v maximum current into any pin .........................................?0ma continuous power dissipation (t a = +70?) 8-pin ?ax (derate 5.9mw/? above +70?) ..........470.6mw 16-pin qsop (derate 8.3mw/? above +70?)........666.7mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) .......................................+260? parameter symbol conditions min typ max units dc accuracy (note 1) resolution 10 bits relative accuracy inl (note 2) ? lsb differential nonlinearity dnl no missing codes over temperature ? lsb offset error ? lsb offset-error temperaturecoefficient relative to fsr 0.3 ppm/ c gain error (note 3) 1 lsb gain-temperature coefficient relative to fsr 0.3 ppm/ c channel-to-channel offsetmatching 0.1 lsb channel-to-channel gainmatching ?.1 lsb dynamic performance (f in(sine-wave) = 10khz, v in(p-p) = v ref , f sample = 94.4ksps) signal-to-noise plus distortion sinad 60 db total harmonic distortion thd up to the 5th harmonic -70 db spurious free dynamic range sfdr 70 db full-power bandwidth sinad > 57db 3.0 mhz full-linear bandwidth -3db point 5.0 mhz conversion rate internal clock 6.8 conversion time (note 4) t conv external clock 10.6 ? internal clock, scan[1:0] = 01 53 internal clock, scan[1:0] = 00cs[3:0] = 1011 (max1138/max1139) 53 throughput rate f sample external clock 94.4 ksps track/hold acquisition time 800 ns downloaded from: http:///
max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs ___________________________________________________ ____________________________________ 3 electrical characteristics (continued) (v dd = 2.7v to 3.6v (max1137/max1139), v dd = 4.5v to 5.5v (max1136/max1138), v ref = 2.048v (max1137/max1139), v ref = 4.096v (max1136/max1138), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?. see tables 1? for programming notation.) parameter symbol conditions min typ max units internal clock frequency 2.8 mhz external clock, fast mode 60 aperture delay (note 5) t ad external clock, high-speed mode 30 ns analog input (ain0?in11) unipolar 0 v ref input-voltage range, single-ended and differential (note 6) bipolar 0 v ref /2 v input multiplexer leakage current on/off leakage current, vain_ = 0 or vdd ?.01 ? ? input capacitance cin 22 pf internal reference (note 7) max1137/max1139 1.968 2.048 2.128 reference voltage vref t a = +25? max1136/max1138 3.939 4.096 4.256 v reference-voltage temperaturecoefficient tcvref 25 ppm/? ref short-circuit current 2m a ref source impedance 1.5 k ? external reference ref input-voltage range vref (note 8) 1 vdd v ref input current iref f sample = 94.4ksps 40 ? digital inputs/outputs (scl, sda) input high voltage v ih 0.7 ? v dd v input low voltage v il 0.3 ? v dd v input hysteresis v hyst 0.1 ? v dd v input current i in v in 0 to v dd 10 ? input capacitance c in 15 pf output low voltage v ol i sink = 3ma 0.4 v power requirements max1137/max1139 2.7 3.6 supply voltage v dd max1136/max1138 4.5 5.5 v internal reference 900 1150 f sample = 94.4ksps external clock external reference 670 900 internal reference 530 f sample = 40ksps internal clock external reference 230 internal reference 380 f sample = 10ksps internal clock external reference 60 internal reference 330 f sample =1ksps internal clock external reference 6 supply current i dd shutdown (internal reference off) 0.5 10 ? downloaded from: http:///
max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs 4 __________________________________________________ _____________________________________ electrical characteristics (continued) (v dd = 2.7v to 3.6v (max1137/max1139), v dd = 4.5v to 5.5v (max1136/max1138), v ref = 2.048v (max1137/max1139), v ref = 4.096v (max1136/max1138), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?. see tables 1? for programming notation.) timing characteristics (figure 1) (v dd = 2.7v to 3.6v (max1137/max1139), v dd = 4.5v to 5.5v (max1136/max1138), v ref = 2.048v (max1137/max1139), v ref = 4.096v (max1136/max1138), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?. see tables 1? for programming notation.) parameter symbol conditions min typ max units power requirements power-supply rejection ratio psrr full-scale input (note 9) 0.01 0.5 lsb/v parameter symbol conditions min typ max units timing characteristics for fast mode serial clock frequency f scl 400 khz bus free time between astop (p) and a start (s) condition t buf 1.3 ? hold time for start (s) condition t hd , sta 0.6 ? low period of the scl clock t low 1.3 ? high period of the scl clock t high 0.6 ? setup time for a repeated start condition (sr) t su , sta 0.6 ? data hold time t hd , dat (note 10) 0 900 ns data setup time t su , dat 100 ns rise time of both sda and sclsignals, receiving t r measured from 0.3v dd to 0.7v dd 20 + 0.1c b 300 ns fall time of sda transmitting t f measured from 0.3v dd to 0.7v dd (note 11) 20 + 0.1c b 300 ns setup time for stop (p) condition t su , sto 0.6 ? capacitive load for each bus line c b 400 pf pulse width of spike suppressed t sp 50 ns timing characteristics for high-speed mode (c b = 400pf, note 12) serial clock frequency f sclh (note 13) 1.7 mhz hold time, repeated start condition (sr) t hd , sta 160 ns low period of the scl clock t low 320 ns high period of the scl clock t high 120 ns setup time for a repeated start condition (sr) t su , sta 160 ns data hold time t hd , dat (note 10) 0 150 ns data setup time t su , dat 10 ns downloaded from: http:///
note 1: for dc accuracy, the max1136/max1138 are tested at v dd = 5v and the max1137/max1139 are tested at v dd = 3v. all devices are configured for unipolar, single-ended inputs. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offsets have been calibrated. note 3: offset nulled. note 4: conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. conversiontime does not include acquisition time. scl is the conversion clock in the external clock mode. note 5: a filter on the sda and scl inputs suppresses noise spikes and delays the sampling instant. note 6: the absolute input-voltage range for the analog inputs (ain0?in11) is from gnd to v dd . note 7: when the internal reference is configured to be available at ain_/ref (sel[2:1] = 11) decouple ain_/ref to gnd with a 0.1? capacitor and a 2k ? series resistor (see the typical operating circuit ). note 8: adc performance is limited by the converter? noise floor, typically 300? p-p . note 9: measured as for the max1137/max1139 and for the max1136/max1138 note 10: a master device must provide a data hold time for sda (referred to v il of scl) in order to bridge the undefined region of scl? falling edge (see figure 1). note 11: the minimum value is specified at +25?. note 12: c b = total capacitance of one bus line in pf. note 13: f scl must meet the minimum clock low time plus the rise/fall times. vvvv v vv fs fs ref n (. ) (. ) (. . ) 55 45 21 55 45 [] ? ? ? ? ? ? vvvv v vv fs fs ref n (. ) (. ) (. . ) 36 27 21 36 27 [] ? ? ? ? ? ? max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs ___________________________________________________ ____________________________________ 5 timing characteristics (figure 1) (continued) (v dd = 2.7v to 3.6v (max1137/max1139), v dd = 4.5v to 5.5v (max1136/max1138), v ref = 2.048v (max1137/max1139), v ref = 4.096v (max1136/max1138), f scl = 1.7mhz, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?. see tables 1? for programming notation.).) parameter symbol conditions min typ max units rise time of scl signal(current source enabled) t rcl measured from 0.3v dd to 0.7v dd 20 80 ns rise time of scl signal afteracknowledge bit t rcl1 measured from 0.3v dd to 0.7v dd 20 160 ns fall time of scl signal t fcl measured from 0.3v dd to 0.7v dd 20 80 ns rise time of sda signal t rda measured from 0.3v dd to 0.7v dd 20 160 ns fall time of sda signal t fda measured from 0.3v dd to 0.7v dd (note 11) 20 160 ns setup time for stop (p) condition t su , sto 160 ns capacitive load for each bus line c b 400 pf pulse width of spike suppressed t sp (notes 10 and 13) 0 10 ns downloaded from: http:///
max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs 6 __________________________________________________ _____________________________________ typical operating characteristics (v dd = 3.3v (max1137/max1139), v dd = 5v (max1136/max1138), f scl = 1.7mhz, external clock, f sample = 94.4ksps, single- ended, unipolar, t a = +25?, unless otherwise noted.) -0.3 -0.1-0.2 0.1 0 0.2 0.3 0 1000 differential nonlinearity vs. digital code max1136 toc01 digital output code dnl (lsb) 400 200 600 800 -0.5 -0.2-0.3 -0.4 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 400 200 600 800 1000 integral nonlinearity vs. digital code max1136 toc02 digital output code inl (lsb) -160 -140 -120 -100 -80 -60 -40 -20 0 0 10k 20k 30k 40k 50k fft plot max1136 toc03 frequency (hz) amplitude (dbc) f sample = 94.4ksps f in = 10khz 300 400350 500450 600550 650 750700 800 -40 -10 5 -25 20 35 50 65 80 supply current vs. temperature max1136 toc04 temperature ( c) supply current ( a) internal reference max1138/1136 max1139/1137 max1138/1136 max1139/1137 internal reference external reference external reference setup byteext ref: 10111011 int ref: 11011011 0 0.20.1 0.40.3 0.5 0.6 2.7 5.2 shutdown supply current vs. supply voltage max1136 toc05 input voltage (v) i dd ( a) 3.7 3.2 4.2 4.7 sda = scl = v dd 0 0.100.05 0.200.15 0.300.25 0.35 0.450.40 0.50 -40 -10 5 -25 20 35 50 65 80 shutdown supply current vs. temperature max1136 toc06 temperature ( c) supply current ( a) max1138 max1139 200 300250 350 400 450 500 550 600 650 700 750 800 0 20 30 40 60 80 100 average supply current vs. conversion rate (external clock) max1136 toc07 conversion rate (ksps) average i dd ( a) 010 50 70 90 a b a) internal reference always onb) external reference max1138 0.9990 0.99940.9992 0.99980.9996 1.00021.0000 1.0004 1.00081.0006 1.0010 -40 -10 5 -25 20 35 50 65 80 internal reference voltage vs. temperature max1136 toc08 temperature ( c) v ref normalized max1138 max1139 normalized to reference value at +25 c 0.99990 0.999940.99992 0.999980.99996 1.000021.00000 1.00004 1.000081.00006 1.00010 2.7 3.3 3.6 3.9 3.0 4.2 4.5 4.8 5.1 5.4 normalized reference voltage vs. supply voltage max1136 toc09 v dd (v) v ref normalized max1138/max1136, normalized to reference value at v dd = 5v max1139/max1137, normalized to reference value at v dd = 3.3v downloaded from: http:///
max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs ___________________________________________________ ____________________________________ 7 typical operating characteristics (continued) (v dd = 3.3v (max1137/max1139), v dd = 5v (max1136/max1138), f scl = 1.7mhz, external clock, f sample = 94.4ksps, single- ended, unipolar, t a = +25?, unless otherwise noted.) -1.0 -0.8-0.9 -0.6-0.7 -0.4-0.5 -0.3 -0.1-0.2 0 -40 -10 5 -25 2035 506580 offset error vs. temperature max1136 toc10 temperature ( c) offset error (lsb) -1.0 -0.8-0.9 -0.6-0.7 -0.4-0.5 -0.3 -0.1-0.2 0 2.7 3.3 3.6 3.9 3.0 4.2 4.5 4.8 5.1 5.4 offset error vs. supply voltage max1136 toc11 v dd (v) offset error (lsb) 0 0.20.1 0.40.3 0.60.5 0.7 0.90.8 1.0 -40 -10 5 -25 2035506580 gain error vs. temperature max1136 toc12 temperature ( c) gain error (lsb) 0 0.30.2 0.1 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2.7 3.7 3.2 4.2 4.7 5.2 gain error vs. supply voltage max1136 toc13 v dd (v) gain error (lsb) downloaded from: http:///
max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs 8 __________________________________________________ _____________________________________ pin description pin max1136max1137 max1138max1139 name function 1, 2, 3 1, 2, 3 ain0?in2 4? ain3?in7 16, 15, 14 ain8?in10 analog inputs 4 ain3/ref analog input 3/reference input or output. selected in the setup register.(see tables 1 and 6.) 13 ain11/ref analog input 11/reference input or output. selected in the setup register.(see tables 1 and 6.) 5 9 scl clock input 6 10 sda data input/output 7 11 gnd ground 81 2v dd positive supply. bypass to gnd with a 0.1? capacitor. t hd.sta t su.dat t high t r t f t hd.dat t hd.sta s sr a scl sda t su.sta t low t buf t su.sto ps t hd.sta t su.dat t high t fcl t hd.dat t hd.sta s sr a scl sda t su.sta t low t buf t su.sto s t rcl t rcl1 hs-mode f/s-mode a. f/s-mode 2-wire serial interface timing b. hs-mode 2-wire serial interface timing t fda t rda t t r t f p figure 1. 2-wire serial interface timing downloaded from: http:///
detailed description the max1136?ax1139 analog-to-digital converters(adcs) use successive-approximation conversion tech- niques and fully differential input track/hold (t/h) cir- cuitry to capture and convert an analog signal to a serial 12-bit digital output. the max1136/max1137 are 4-channel adcs, and the max1138/max1139 are 12-channel adcs. these devices feature a high-speed 2-wire serial interface supporting data rates up to 1.7mhz. figure 2 shows the simplified internal structurefor the max1138/max1139. power supply the max1136?ax1139 operates from a single supplyand consumes 670? (typ) at sampling rates up to 94.4ksps. the max1137/max1139 feature a 2.048v internal reference and the max1136/max1138 feature a 4.096v internal reference. all devices can be config- ured for use with an external reference from 1v to v dd . analog input and track/hold the max1136?ax1139 analog-input architecture con-tains an analog-input multiplexer (mux), a fully differen- tial track-and-hold (t/h) capacitor, t/h switches, a comparator, and a fully differential switched capacitive digital-to-analog converter (dac) (figure 4). in single-ended mode the analog-input multiplexer con- nects c t/h between the analog input selected by cs[3:0] (see the configuration/setup bytes section) and gnd (table 3). in differential mode, the analog-input multiplexer connects c t/h to the ??and ??ana- log inputs selected by cs[3:0] (table 4). during the acquisition interval the t/h switches are in the track position and c t/h charges to the analog input max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs ___________________________________________________ ____________________________________ 9 analog input mux ain1 ain11/ref ain2 ain3 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain0 scl sda input shift register setup register configuration register control logic reference 4.096v (max1138)2.048v (max1139) internal oscillator output shift register and ram ref t/h 10-bit adc v dd gnd max1138max1139 figure 2. max1138/max1139 functional diagram v dd i ol i oh v out 400pf sda figure 3. load circuit downloaded from: http:///
max1136?ax1139 signal. at the end of the acquisition interval, the t/hswitches move to the hold position retaining the charge on c t/h as a stable sample of the input signal. during the conversion interval, the switched capacitivedac adjusts to restore the comparator input voltage to 0v within the limits of 10-bit resolution. this action requires 10 conversion clock cycles and is equivalent to transferring a charge of 11pf ? (v in+ - v in- ) from c t/h to the binary weighted capacitive dac, forming a digital representation of the analog input signal.sufficiently low source impedance is required to ensure an accurate sample. a source impedance of up to 1.5k ? does not significantly degrade sampling accuracy. tominimize sampling errors with higher source impedances, connect a 100pf capacitor from the analog input to gnd. this input capacitor forms an rc filter with the source impedance limiting the analog-input bandwidth. for larg- er source impedances, use a buffer amplifier to maintain analog-input signal integrity and bandwidth. when operating in internal clock mode, the t/h circuitry enters its tracking mode on the eighth rising clock edge of the address byte (see the slave address section). the t/h circuitry enters hold mode on the falling clock edge ofthe acknowledge bit of the address byte (the ninth clock pulse). a conversion, or series of conversions, are then internally clocked and the max1136?ax1139 holds scl low. with external clock mode, the t/h circuitry enters track mode after a valid address on the rising edge of the clock during the read (r/ w = 1) bit. hold mode is then entered on the rising edge of the second clock pulse during the shifting out of the first byte of theresult. the conversion is performed during the next 10 clock cycles. the time required for the t/h circuitry to acquire an input signal is a function of the input sample capaci- tance. if the analog-input source impedance is high, the acquisition time constant lengthens and more time must be allowed between conversions. the acquisition time (t acq ) is the minimum time needed for the signal to be acquired. it is calculated by: t acq 9 ? (r source + r in ) ? c in where r source is the analog-input source impedance, r in = 2.5k ? , and c in = 22pf. t acq is 1.5/f scl for internal clock mode and t acq = 2/f scl for external clock mode. analog input bandwidth the max1136?ax1139 feature input-tracking circuitrywith a 5mhz small-signal bandwidth. the 5mhz input bandwidth makes it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adc? sampling rate by using under sampling techniques. to avoid high-fre- quency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. analog input range and protection internal protection diodes clamp the analog input tov dd and gnd. these diodes allow the analog inputs to 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs 10 _________________________________________________ _____________________________________ track track hold c t/h c t/h track track hold ain0 ain1 ain2 ain3/ref gnd analog input mux capacitive dac ref capacitive dac ref max1136max1137 hold hold track hold v dd /2 figure 4. equivalent input circuit downloaded from: http:///
swing from (gnd - 0.3v) to (v dd + 0.3v) without caus- ing damage to the device. for accurate conversionsthe inputs must not go more than 50mv below gnd or above v dd . single-ended/differential input the sgl/ dif of the configuration byte configures the max1136?ax1139 analog-input circuitry for single-ended or differential inputs (table 2). in single-ended mode (sgl/ dif = 1), the digital conversion results are the difference between the analog input selected by cs[3:0]and gnd (table 3). in differential mode (sgl/ dif = 0) the digital conversion results are the difference between the??and the ??analog inputs selected by cs[3:0] (table 4). unipolar/bipolar when operating in differential mode, the bip/ uni bit of the setup byte (table 1) selects unipolar or bipolaroperation. unipolar mode sets the differential input range from 0 to v ref . a negative differential analog input in unipolar mode will cause the digital outputcode to be zero. selecting bipolar mode sets the differ- ential input range to ? ref /2. the digital output code is binary in unipolar mode and two? complement in bipo-lar mode, see the transfer functions section. in single-ended mode the max1136?ax1139 willalways operate in unipolar mode irrespective of bip/ uni . the analog inputs are internally referenced to gnd with a full-scale input range from 0 to v ref . 2-wire digital interface the max1136?ax1139 feature a 2-wire interface con-sisting of a serial data line (sda) and serial clock line (scl). sda and scl facilitate bidirectional communica- tion between the max1136?ax1139 and the master at rates up to 1.7mhz. the max1136?ax1139 are slaves that transfer and receive data. the master (typically a microcontroller) initiates data transfer on the bus and generates the scl signal to permit that transfer. sda and scl must be pulled high. this is typically done with pullup resistors (750 ? or greater) (see the typical operating circuit ). series resistors (r s ) are optional. they protect the input architecture of the max1136max1139 from high voltage spikes on the bus lines, min- imize crosstalk, and undershoot of the bus signals. bit transfer one data bit is transferred during each scl clockcycle. a minimum of eighteen clock cycles are required to transfer the data in or out of the max1136?ax1139. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is stable are considered control signals (see the start and stop conditions section). both sda and scl remain high when the bus is not busy. start and stop conditions the master initiates a transmission with a start condi-tion (s), a high-to-low transition on sda while scl is high. the master terminates a transmission with a stop condi- tion (p), a low-to-high transition on sda while scl is high (figure 5). a repeated start condition (sr) can be used in place of a stop condition to leave the bus active and the mode unchanged (see hs-mode). acknowledge bits data transfers are acknowledged with an acknowledgebit (a) or a not-acknowledge bit ( a ). both the master and the max1136?ax1139 (slave) generate acknowl-edge bits. to generate an acknowledge, the receiving device must pull sda low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (figure 6). to generate a not-acknowledge, the receiv- er allows sda to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves sda high during the high period of the clock pulse. monitoring the acknowledge bits allows for detection of unsuccessful data transfers. an unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. in the event of an unsuc- cessful data transfer the bus master should reattempt communication at a later time. max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs ___________________________________________________ ___________________________________ 11 scl sda sp sr figure 5. start and stop conditions scl sda s not acknowledge acknowledge 12 89 figure 6. acknowledge bits downloaded from: http:///
max1136?ax1139 slave address a bus master initiates communication with a slave deviceby issuing a start condition followed by a slave address. when idle, the max1136?ax1139 continuous- ly wait for a start condition followed by their slave address. when the max1136?ax1139 recognize their slave address, they are ready to accept or send data. the slave address has been factory programmed and is always 0110100 for the max1136/max1137, and 0110101 for max1138/max1139 (figure 7). the least sig- nificant bit (lsb) of the address byte (r/ w ) determines whether the master is writing to or reading from themax1136?ax1139 (r/ w = 0 selects a write condition, r/ w = 1 selects a read condition). after receiving the address, the max1136?ax1139 (slave) issues anacknowledge by pulling sda low for one clock cycle. bus timing at power-up, the max1136?ax1139 bus timing is setfor fast mode (f/s-mode) which allows conversion rates up to 22.2ksps. the max1136?ax1139 must operatein high-speed mode (hs-mode) to achieve conversion rates up to 94.4ksps. figure 1 shows the bus timing for the max1136?ax1139? 2-wire interface. hs-mode at power-up, the max1136?ax1139 bus timing is setfor f/s-mode. the bus master selects hs-mode by addressing all devices on the bus with the hs-mode master code 0000 1xxx (x = don? care). after success- fully receiving the hs-mode master code, the max1136?ax1139 issue a not-acknowledge allowing sda to be pulled high for one clock cycle (figure 8). after the not-acknowledge, the max1136?ax1139 are in hs-mode. the bus master must then send a repeated start followed by a slave address to initiate hs-mode communication. if the master generates a stop condi- tion the max1136?ax1139 returns to f/s-mode. 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs 12 _________________________________________________ _____________________________________ 01 1 1 0 0 0 r/w a slave address max1136/max1137 s scl sda 123456789 device slave address 01101000110101 max1136/max1137max1138/max1139 figure 7. max1136/max1137 slave address byte 000 1 0x x x a hs-mode master code scl sda s sr f/s-mode hs-mode figure 8. f/s-mode to hs-mode transfer downloaded from: http:///
configuration/setup bytes (write cycle) a write cycle begins with the bus master issuing astart condition followed by seven address bits (figure 7) and a write bit (r/ w = 0). if the address byte is suc- cessfully received, the max1136?ax1139 (slave)issues an acknowledge. the master then writes to the slave. the slave recognizes the received byte as the setup byte (table 1) if the most significant bit (msb) is 1. if the msb is 0, the slave recognizes that byte as the configuration byte (table 2). the master can write eitherone or two bytes to the slave in any order (setup byte then configuration byte; configuration byte then setup byte; setup byte or configuration byte only; figure 9). if the slave receives a byte successfully, it issues an acknowledge. the master ends the write cycle by issu- ing a stop condition or a repeated start condition. when operating in hs-mode, a stop condition returns the bus into f/s-mode (see the hs-mode section). max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs ___________________________________________________ ___________________________________ 13 b. two-byte write cycle slave to master master to slave s 1 slave address a 71 1 w setup or configuration byte setup or configuration byte 8 p or sr 1 a 1 msb determines whether setup or configuration byte s 1 slave address a 71 1 w setup or configuration byte 8 p or sr 1 a 1 msb determines whether setup or configuration byte a 1 8 a. one- byte write cycle number of bits number of bits figure 9. write cycle bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) reg sel2 sel1 sel0 clk bip/ uni rst x bit name description 7 reg register bit. 1 = setup byte, 0 = configuration byte (see table 2). 6 sel2 5 sel1 4 sel0 three bits select the reference voltage and the state of ain_/ref (table 6). defaulted to 000 atpower-up. 3 clk 1 = external clock, 0 = internal clock. defaulted to 0 at power-up. 2 bip/ uni 1 = bipolar, 0 = unipolar. defaulted to 0 at power-up. 1 rst 1 = no action, 0 = resets the configuration register to default. setup register remains unchanged. 0 x don? care, can be set to 1 or 0. table 1. setup byte format downloaded from: http:///
max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs 14 _________________________________________________ _____________________________________ bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) reg scan1 scan0 cs3 cs2 cs1 cs0 sgl/ dif bit name description 7 reg register bit 1= setup byte (see table 1), 0 = configuration byte 6 scan1 5 scan0 scan select bits. two bits select the scanning configuration(table 5). defaulted to 00 at power-up. 4 cs3 3 cs2 2 cs1 1 cs0 channel select bits. four bits select which analog input channels are to be used for conversion(tables 3 and 4). defaulted to 0000 at power-up. for max1136/max1137, cs3 and cs2 are internally set to 0. 0s g l / dif 1 = single-ended, 0 = differential (tables 3 and 4). defaulted to 1 at power-up. see the single- ended/differential input section. table 2. configuration byte format cs3 1 cs2 1 cs1 cs0 ain0 ain1 ain2 ain3 2 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain11 2 gnd 0000+ - 0001 + - 0010 + - 0011 + - 0100 + - 0101 + - 0110 + - 0111 + - 1000 + - 1001 +- 1010 +- 1011 + - 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved 1. for max1136/max1137, cs3 and cs2 are internally set to 0. 2. when sel1 = 1, a single-ended read of ain3/ref (max1136/max1137) or ain11/ref (max1138/max1139) will be ignored; scan will stop at ain2 or ain10. table 3. channel selection in single-ended mode (sgl/ dif = 1) downloaded from: http:///
data byte (read cycle) a read cycle must be initiated to obtain conversionresults. read cycles begin with the bus master issuing a start condition followed by seven address bits and a read bit (r/ w = 1). if the address byte is successfully received, the max1136?ax1139 (slave) issues anacknowledge. the master then reads from the slave. the result is transmitted in two bytes; first six bits of the first byte are high, then msb through lsb are consecu- tively clocked out. after the master has received the byte(s) it can issue an acknowledge if it wants to con- tinue reading or a not-acknowledge if it no longer wish- es to read. if the max1136?ax1139 receive a not- acknowledge, they release sda allowing the master to generate a stop or a repeated start condition. see the clock mode and scan mode sections for detailed information on how data is obtained and converted. clock modes the clock mode determines the conversion clock andthe data acquisition and conversion time. the clock mode also affects the scan mode. the state of the set- up byte? clk bit determines the clock mode (table 1). at power-up the max1136?ax1139 are defaulted tointernal clock mode (clk = 0). internal clock when configured for internal clock mode (clk = 0), themax1136?ax1139 use their internal oscillator as the con- version clock. in internal clock mode, the max1136 max1139 begin tracking the analog input after a valid address on the eighth rising edge of the clock. on the falling edge of the ninth clock the analog signal is acquired and the conversion begins. while converting the analog input signal, the max1136?ax1139 holds scl low (clock stretching). after the conversion completes, the results are stored in internal memory. if the scan mode is set for multi- ple conversions, they will all happen in succession with each additional result stored in memory.the max1136/max1137 contain four 10-bit blocks of memory, and the max1138/max1139 contain twelve 10-bit blocks of memory. once all conversions are complete, the max1136?ax1139 release scl allowing it to be pulled high. the master may now clock the results out of the memory in the same order the scan conversion has been done at a clock rate of up to 1.7mhz. scl will be stretched for a maximum of 7.6? per channel (see figure 10). max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs ___________________________________________________ ___________________________________ 15 cs3 1 cs2 1 cs1 cs0 ain0 ain1 ain2 ain3 2 ain4 ain5 ain6 ain7 ain8 ain9 ain10 ain11 2 0000+ - 0001 -+ 0010 + - 0011 - + 0100 + - 0101 - + 0110 + - 0111 -+ 1000 +- 1001 -+ 1010 +- 1011 -+ 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 reserved 1 1 1 1 reserved 1. for max1136/max1137, cs3 and cs2 are internally set to 0. 2. when sel1 = 1, a differential read between ain2 and ain3/ref (max1136/max1137) or ain10 and ain11/ref (max1138/max1139) will return the difference between gnd and ain2 or ain10, respectively. for example, a differential read of 1011 will return the negative difference between ain10 and gnd. in differential scanning, the address increments by 2 until lim it set by cs3:cs1 has been reached. table 4. channel selection in differential mode (sgl/ dif = 0) downloaded from: http:///
max1136?ax1139 the device memory contains all of the conversion results when the max1136?ax1139 release scl. theconverted results are read back in a first-in-first-out (fifo) sequence. if ain_/ref is set to be a reference input or output (sel1 = 1, table 6), ain_/ref will be excluded from a multichannel scan. the memory con- tents can be read continuously. if reading continuespast the result stored in memory, the pointer will wrap around and point to the first result. note that only the current conversion results will be read from memory.the device must be addressed with a read command to obtain new conversion results. the internal clock mode? clock stretching quiets the scl bus signal reducing the system noise during con- version. using the internal clock also frees the bus master (typically a microcontroller) from the burden of running the conversion clock, allowing it to perform other tasks that do not need to use the bus. 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs 16 _________________________________________________ _____________________________________ b. scan mode conversions with internal clock s 1 slave address a 71 1 r clock stretch number of bits p or sr 1 8 result 8 lsbs 8 result 2 msbs a a 1 a. single conversion with internal clock s 1 slave address 71 1 r clock stretch a number of bits p or sr 1 8 result 1 ( 2msbs) a 1 a 8 result 1 (8 lsbs) a 8 result n (8lsbs) a 1 8 result n (8msbs) slave to master master to slave clock stretch t acq1 t conv2 t acq2 t convn t acqn t conv t acq 1 1 t conv1 figure 10. internal clock mode read cycles slave address t conv1 t acq1 t acq2 t convn t acqn t conv t acq number of bits number of bits 1 8 a 1 s 1 a 71 1 r s 1 71 1 r p or sr 1 8 a 1 a 8 a 8 b. scan mode conversions with external clock 1 1 slave address p or sr result (8 lsbs) 8 a 1 result (2 msbs) a. single conversion with external clock slave to master master to slave result 1 (2 msbs) result 2 (8 lsbs) result n (8 lsbs) a 1 8 result n (2 msbs) a figure 11. external clock mode read cycle downloaded from: http:///
external clock when configured for external clock mode (clk = 1),the max1136?ax1139 use the scl as the conversion clock. in external clock mode, the max1136?ax1139 begin tracking the analog input on the ninth rising clock edge of a valid slave address byte. two scl clock cycles later the analog signal is acquired and the con- version begins. unlike internal clock mode, converted data is available immediately after the first four empty high bits. the device will continuously convert input channels dictated by the scan mode until given a not acknowledge. there is no need to re-address the device with a read command to obtain new conversion results (see figure 11). the conversion must complete in 1ms or droop on the track-and-hold capacitor will degrade conversion results. use internal clock mode if the scl clock period exceeds 60s. the max1136?ax1139 must operate in external clock mode for conversion rates from 40ksps to 94.4ksps. below 40ksps internal clock mode is recommended due to much smaller power consumption. scan mode scan0 and scan1 of the configuration byte set thescan mode configuration. table 5 shows the scanning configurations. if ain_/ref is set to be a reference input or output (sel1 = 1, table 6), ain_/ref will be excluded from a multichannel scan. the scanned results are written to memory in the same order as the conversion. read the results from memory in the orderthey were converted. each result needs a 2-byte trans- mission, the first byte begins with six empty bits during which sda is left high. each byte has to be acknowl- edged by the master or the memory transmission will be terminated. it is not possible to read the memoryindependently of conversion. applications information power-on reset the configuration and setup registers (tables 1 and 2)will default to a single-ended, unipolar, single-channel conversion on ain0 using the internal clock with v dd as the reference and ain_/ref configured as an analoginput. the memory contents are unknown after power-up. automatic shutdown automatic shutdown occurs between conversions whenthe max1136?ax1139 are idle. all analog circuits participate in automatic shutdown except the internal reference due to its prohibitively long wake-up time. when operating in external clock mode, a stop, not- acknowledge or repeated start, condition must be issued to place the devices in idle mode and benefit from automatic shutdown. a stop condition is not nec- essary in internal clock mode to benefit from automatic shutdown because power-down occurs once all con- version results are written to memory (figure 10). when using an external reference or v dd as a reference, all analog circuitry is inactive in shutdown and supply cur- rent is less than 0.5a (typ). the digital conversion results obtained in internal clock mode are maintained in memory during shutdown and are available for access through the serial interface at any time prior to astop or a repeated start condition. when idle the max1136?ax1139 continuously wait for a start condition followed by their slave address (see slave address section). upon reading a valid address byte the max1136?ax1139 power-up. theinternal reference requires 10ms to wake up, so when using the internal reference it should be powered up max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs ___________________________________________________ ___________________________________ 17 scan1 scan0 scanning configuration 00 s cans up fr om ain 0 to the i np ut sel ected b y c s 3c s 0. when c s 3c s 0 exceed s 1011, the scanni ng w i l l stop at ain 11. when ain _/re f i s set to b e a r efer ence i np ut/outp ut, scanni ng w i l l stop at ain 2 and ain 10. 0 1 *converts the input selected by cs3?s0 eight times. (see tables 3 and 4) scans up from ain2 to the input selected by cs1 and cs0. when cs1 and cs0 are set for ain0?in2,the only scan that takes place is ain2 (max1136/max1137). when ain/ref is set to be a reference input/output, scanning stops at ain2. 10 scans up from ain6 to the input selected by cs3?s0. when cs3?s0 is set for ain0?in6, the onlyscan that takes place is ain6 (max1138/max1139). when ain/ref is set to be a reference input/ output, scanning stops at selected channel or ain10. 1 1 *converts channel selected by cs3?s0. * when operating in external clock mode there is no difference between scan[1:0] = 01 and scan[1:0] = 11 and converting will occu r perpetually until not acknowledge occurs. table 5. scanning configuration downloaded from: http:///
max1136?ax1139 10ms prior to conversion or powered continuously.wake-up is invisible when using an external reference or v dd as the reference. automatic shutdown results in dramatic power savings,particularly at slow conversion rates and with internal clock. for example, at a conversion rate of 10ksps, the average supply current for the max1137 is 60? (typ) and drops to 6? (typ) at 1ksps. at 0.1ksps the average sup- ply current is just 1?, or a minuscule 3? of power con- sumption, see average supply current vs. conversion rate in the typical operating characteristics . reference voltage sel[2:0] of the setup byte (table 1) control the referenceand the ain_/ref configuration (table 6). when ain_/ref is configured to be a reference input or reference output (sel1 = 1), differential conversions on ain_/ref appear as if ain_/ref is connected to gnd (see note 2 and table 4). single-ended conversion in scan mode on ain_/ref will be ignored by internal limiter, which sets the highest available channel at ain2 or ain10. internal reference the internal reference is 4.096v for the max1136/max1138 and 2.048v for the max1137/max1139. sel1 of the setup byte controls whether ain_/ref is used for an analog input or a reference (table 6). when ain_/ref is configured to be an internal reference output (sel[2:1] = 11), decouple ain_/ref to gnd with a 0.1? capacitor and a 2k ? sereis resistor (see the typical operating circuit ). once powered up, the reference always remains on until reconfigured. the internal reference requires 10msto wake up and is accessed using sel0 (table 6). when in shutdown, the internal reference output is in a high- impedance state. the reference should not be used to supply current for external circuitry. the internal reference does not require an external bypass capacitor and works best when not connected to the pin (sel1 = 0). external reference the external reference can range from 1v to v dd . for maximum conversion accuracy, the reference must be able to deliver up to 40? and have an output imped-ance of 500 ? or less. if the reference has a higher out- put impedance or is noisy, bypass it to gnd as close toain_/ref as possible with a 0.1? capacitor. transfer functions output data coding for the max1136?ax1139 is bina-ry in unipolar mode and two? complement in bipolar mode with 1 lsb = (v ref /2n) where ??is the number of bits (10). code transitions occur halfway betweensuccessive-integer lsb values. figure 12 and figure 13 show the input/output (i/o) transfer functions for unipolar and bipolar operations, respectively. layout, grounding, and bypassing only use pc boards. wire-wrap configurations are notrecommended since the layout should ensure proper separation of analog and digital traces. do not run ana- log and digital lines parallel to each other, and do not layout digital signal paths underneath the adc pack- 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs 18 _________________________________________________ _____________________________________ sel2 sel1 sel0 reference voltage ain_/ref internal reference state 00x v dd analog input always off 0 1 x external reference reference input always off 1 0 0 internal reference analog input always off 1 0 1 internal reference analog input always on 1 1 0 internal reference reference output always off 1 1 1 internal reference reference output always on table 6. reference voltage and ain_/ref format output code full-scale transition 11 . . . 111 11 . . . 110 11 . . . 101 00 . . . 01100 . . . 010 00 . . . 001 00 . . . 000 123 0 fs fs - 3/2 lsb fs = v ref zs = gnd input voltage (lsb) 1 lsb = v ref 1024 max1136 max1139 figure 12. unipolar transfer function downloaded from: http:///
age. use separate analog and digital pc board groundsections with only one star point (figure 14) connecting the two ground systems (analog and digital). for lowest noise operation, ensure the ground return to the star ground? power supply is low impedance and as short as possible. route digital signals far away from sensi- tive analog and reference inputs. high-frequency noise in the power supply (v dd ) could influence the proper operation of the adc? fast com-parator. bypass v dd to the star ground with a network of two parallel capacitors, 0.1? and 4.7?, located asclose as possible to the max1136?ax1139 power-sup- ply pin. minimize capacitor lead length for best supply noise rejection, and add an attenuation resistor (5 ? ) in series with the power supply, if it is extremely noisy. definitions integral nonlinearity integral nonlinearity (inl) is the deviation of the values onan actual transfer function from a straight line. this straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. the max1136 max1139? inl is measured using the endpoint. differential nonlinearity differential nonlinearity (dnl) is the difference betweenan actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes and a monotonic transfer function. aperture jitter aperture jitter (t aj ) is the sample-to-sample variation in the time between the samples. aperture delay aperture delay (t ad ) is the time between the falling edge of the sampling clock and the instant when anactual sample is taken. signal-to-noise ratio for a waveform perfectly reconstructed from digital sam-ples, the theoretical maximum snr is the ratio of the full- scale analog input (rms value) to the rms quantization error (residual error). the ideal, theoretical minimum ana- log-to-digital noise is caused by quantization error only and results directly from the adc? resolution (n bits): snr max[db] = 6.02 db ? n + 1.76 db in reality, there are other noise sources besides quanti-zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five har- monics, and the dc offset. signal-to-noise plus distortion signal-to-noise plus distortion (sinad) is the ratio of thefundamental input frequency? rms amplitude to rms equivalent of all other adc output signals. sinad (db) = 20 ? log (signalrms/noiserms) max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs ___________________________________________________ ___________________________________ 19 011 . . . 111011 . . . 110 000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101 100 . . . 001100 . . . 000 - fs 0 input voltage (lsb) output code zs = 0 +fs - 1 lsb note: v com v ref / 2 v in = (ain+) - (ain-) fs = v ref 2 -fs = -v ref 2 max1136 max1139 1 lsb = v ref 1024 figure 13. bipolar transfer function gnd v logic = 3v/5v 3v or 5v supplies dgnd 3v/5v gnd *optional 4.7 f r* = 5 ? 0.1 f v dd digital circuitry max1136 max1139 figure 14. power-supply grounding connection downloaded from: http:///
effective number of bits effective number of bits (enob) indicates the globalaccuracy of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quanti- zation noise only. with an input range equal to the adc? full-scale range, calculate the enob as follows: enob = (sinad - 1.76)/6.02 total harmonic distortion total harmonic distortion (thd) is the ratio of the rmssum of the input signal? first five harmonics to the fun- damental itself. this is expressed as: where v 1 is the fundamental amplitude, and v 2 through v 5 are the amplitudes of the 2nd through 5th order harmonics. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rmsamplitude of the fundamental (maximum signal compo- nent) to the rms value of the next largest distortion component. thd vvvv v = +++ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 20 2 2 3 2 4 2 5 2 1 log sinad db signalrms noiserms thdrms ( ) log = + ? ? ? ? ? ? 20 max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs 20 _________________________________________________ _____________________________________ downloaded from: http:///
max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs ___________________________________________________ ___________________________________ 21 *optional**ain11/ref (max1138/max1139) *r s *r s analog inputs rc network* c sda scl gnd v dd sda scl ain0ain1 ain3/ref** 3.3v or 5v 2k ? 0.1 f 0.1 f 5v r p c ref r p 5v max1136 max1137 max1138 max1139 typical operating circuit sda scl ain3/ref 1 + + 2 8 7 v dd gnd ain1 ain2 ain0 max top view 3 4 6 5 max1136max1137 1615 14 13 12 11 10 9 12 34 5 6 7 8 ain0 ain8 ain9ain10 ain11/ref v dd gndsda scl max1138max1139 qsop ain1ain2 ain5 ain3ain4 ain6 ain7 pin configurations chip information process: bicmos package type package code document no. 8 ?ax u8+1 21-0036 16 qsop e16+4 21-0055 package information for the latest package outline information and land patterns(footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only.package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. downloaded from: http:///
max1136?ax1139 2.7v to 3.6v and 4.5v to 5.5v, low-power, 4-/12-channel, 2-wire serial 10-bit adcs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 5 5/09 discontinued some versions of the family 1?, 13, 17?1 6 3/10 changed absolute maximum ratings and timing diagram 2, 12 downloaded from: http:///

▲Up To Search▲

Price & Availability of MAX1137MEUA

	To Download MAX1137MEUA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .